9DBV0841 Datasheet, PDF (9/16 Pages) Integrated Circuit Systems – HCSL compatible differential input

9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL
Characterisitics
TA = T_COM or T_IND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
PLL Bandwidth
PLL Jitter Peaking
Duty Cycle
BW
t_JPEAK
t_DC
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
Measured differentially, PLL Mode
2
2.7
4
1
1.4
2
1.2
2
45
50.1
55
UNITS
MHz
MHz
dB
%
NOTES
1,5
1,5
1
1
Duty Cycle Distortion
t_DCD Measured differentially, Bypass Mode @100MHz -1
0
1
%
1,3
Skew, Input to Output
t_pdBYP
t_pdPLL
Bypass Mode, V_T = 50%
PLL Mode V_T = 50%
3000
3600
4500
ps
1
0
92
200
ps
1,4
Skew, Output to Output
t_sk3
V_T = 50%
28
50
ps
1,4
Jitter, Cycle to cycle
t_jcyc-cyc
PLL mode
Additive Jitter in Bypass Mode
16
50
0.1
25
ps
1,2
ps
1,2
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured from differential waveform}
3 _{Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.}
4 _{All outputs at default slew rate}
5 _{The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.}
Electrical Characteristics–Phase Jitter Parameters
TA = T_COM or T_IND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
LIMIT UNITS Notes
t_jphPCIeG1
Phase Jitter, PLL Mode
t_jphPCIeG2
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
34
52
0.9
1.4
2.2
2.5
86 ps (p-p) 1,2,3
3
ps
1,2
(rms)
3.1
ps
(rms)
1,2
t_jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.5
0.6
1
ps _1,2,4
(rms)
t_jphSGMII
125MHz, 1.5MHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
1.9
2
NA
ps
1,6
(rms)
t_jphPCIeG1
PCIe Gen 1
0.6
5
N/A
Additive Phase Jitter,
Bypass Mode
t_jphPCIeG2
t_jphPCIeG3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.1
0.3
N/A
0.05
0.1
N/A
0.05
0.1
N/A
125MHz, 1.5MHz to 10MHz, -20dB/decade
t_{jphSGMII rollover < 1.5MHz, -40db/decade rolloff > 10MHz}
0.15
0.3
N/A
1 _{Applies to all outputs, with device driven by 9FG432AKLF or equivalent.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{Subject to final radification by PCI SIG.}
5 _{For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]}
6 _{Applies to all differential outputs}
ps (p-p) 1,2,3
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
1,2,5
1,2,5
1,2,4,
5
1,6
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
9
9DBV0841
REV C 081214