9DBV0841 Datasheet, PDF (3/16 Pages) Integrated Circuit Systems – HCSL compatible differential input

9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
1 vSADR_tri
LATCHED _{Tri-level latch to select SMBus Address. See SMBus Address Selection Table.}
IN
2 ^vHIBW_BYPM_LOBW# ^{LATCHED Trilevel input to select High BW, Bypass or Low BW mode.}
IN See PLL Operating Mode Table for Details.
3 FB_DNC
DNC
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
4 FB_DNC#
DNC
Complement clock of differential feedback. The feedback output and feedback
input are connected internally on this pin. Do not connect anything to this pin.
5 VDDR1.8
6 CLK_IN
7 CLK_IN#
8 GNDR
9 GNDDIG
PWR
IN
IN
GND
GND
1.8V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG1.8
13 VDDIO
14 vOE0#
IN
I/O
PWR
PWR
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
1.8V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
15 DIF0
16 DIF0#
17 vOE1#
18 DIF1
19 DIF1#
OUT
OUT
IN
OUT
OUT
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
20 VDD1.8
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 vOE2#
PWR
PWR
GND
OUT
OUT
IN
Power supply, nominal 1.8V
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
26 DIF3
27 DIF3#
28 vOE3#
29 GNDA
30 VDDA1.8
31 VDDIO
32 DIF4
33 DIF4#
34 vOE4#
35 DIF5
36 DIF5#
OUT
OUT
IN
GND
PWR
PWR
OUT
OUT
IN
OUT
OUT
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
1.8V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
37 vOE5#
38 VDD1.8
IN
PWR
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 1.8V
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
3
9DBV0841
REV C 081214