9DBV0841 Datasheet, PDF (7/16 Pages) Integrated Circuit Systems – HCSL compatible differential input

9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T_COM or T_IND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
1.8V Supply Voltage
VDD
Supply voltage for core, analog and LVCMOS
outputs
IO Supply Voltage
VDDIO Supply voltage for differential Low Power Outputs
Ambient Operating
Temperature
Input High Voltage
Input Mid Voltage
Input Low Voltage
Schmitt Trigger Postive
Going Threshold Voltage
T_COM
T_IND
V_IH
V_IM
V_IL
V_T+
Commmercial range
Industrial range
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, where indicated
Schmitt Trigger Negative
Going Threshold Voltage
V_T-
Single-ended inputs, where indicated
Hysteresis Voltage
Output High Voltage
Outputt Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
V_H
V_IH
V_IL
I_IN
I_INP
F_ibyp
F_ipll100
F_ipll125
F_ipll156
L_pin
C_IN
C_{INDIF_IN}
C_OUT
T_STAB
V_T+ - V_T-
Single-ended outputs, except SMBus. I_OH = -2mA
Single-ended outputs, except SMBus. I_OL = -2mA
Single-ended inputs, V_IN = GND, V_IN = VDD
Single-ended inputs
V_IN = 0 V; Inputs with internal pull-up resistors
V_IN = VDD; Inputs with internal pull-down resistors
Bypass mode
100MHz PLL mode
125MHz PLL mode
156.25MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency
f_MODIN
Allowable Frequency
(Triangular Modulation)
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
t_F
t_R
V_ILSMB
V_IHSMB
V_OLSMB
I_PULLUP
V_DDSMB
t_RSMB
t_FSMB
f_MAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
V_DDSMB = 3.3V, see note 4 for V_DDSMB < 3.3V
V_DDSMB = 3.3V, see note 5 for V_DDSMB < 3.3V
@ I_PULLUP
@ V_OL
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
4 _{For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB}
5 _{For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB}
6_{DIF_IN input}
7_{The differential input clock must be running for the SMBus to be active}
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
1.7
0.9975
0
-40
0.75 V_DD
0.4 V_DD
-0.3
0.4 V_DD
0.1 V_DD
0.1 V_DD
V_DD-0.45
-5
-200
1
60
75
93.75
1.5
1.5
30
1
2.1
4
1.7
7
1.8
1.9
V
1
1.05
1.9
V
1
25
70
°C
1
25
85
°C
1
V_DD + 0.3 V
1
0.6 V_DD
V
1
0.25 V_DD V
1
0.7 V_DD
V
1
0.4 V_DD
V
1
0.4 V_DD
V
1
V
1
0.45
V
1
5
uA
1
200
uA
1
200
MHz
2
100.00 110
MHz
2
125.00 137.5 MHz
2
156.25 171.875 MHz
2
7
nH
1
5
pF
1
2.7
pF
1,6
6
pF
1
0.600
1
ms
1,2
31.500
33
kHz
1
3
clocks 1,3
300
us
1,3
5
ns
1,2
5
ns
1,2
0.8
V
1,4
3.6
V
1,5
0.4
V
1
mA
1
3.6
V
1
1000
ns
1
300
ns
1
400
kHz 1,7
9DBV0841
REV C 081214