9DBV0841 Datasheet, PDF (8/16 Pages) Integrated Circuit Systems – HCSL compatible differential input

9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
TA = T_COM or T_IND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Slew rate matching
SYMBOL
Trf
ΔTrf
CONDITIONS
Scope averaging on 3.0V/ns setting
Scope averaging on 2.0V/ns setting
Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
1.1
2
1.9
3
7
3 ^V/ns 1, 2, 3
4 V/ns 1, 2, 3
20
% 1, 2, 4
Voltage High
Voltage Low
V_HIGH
V_LOW
Statistical measurement on single-ended signal _{660 774 850}
1,7
using oscilloscope math function. (Scope
mV
averaging on)
-150 18 150
1,7
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
-300
821
-15
1150 _mV
1
1
Vswing
Vswing
Scope averaging off
300 1536
mV 1,2,7
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 414 550 mV 1,5,7
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
13 140 mV 1, 6
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured from differential waveform}
3 _{Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around}
differential 0V.
4 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on}
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 _{Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising}
edge (i.e. Clock rising and Clock# falling).
6 _{The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross}
absolute) allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.
7 _{At default SMBus settings.}
Electrical Characteristics–Current Consumption
TA = T_COM or T_IND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
I_DDAOP
VDDA+VDDR, PLL Mode, @100MHz
Operating Supply Current
I_DDOP
VDD1.8, All outputs active @100MHz
I_DDIOOP
VDDIO, All outputs active @100MHz
I_DDAPD
VDDA+VDDR, PLL Mode, @100MHz
Powerdown Current
I_DDPD
VDD1.8, Outputs Low/Low
I_DDIODZ
VDDIO,Outputs Low/Low
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input clock stopped.}
11
15
8
10
28
35
0.7
1
1.2
2
0.005
0.01
UNITS
mA
mA
mA
mA
mA
mA
NOTES
1
1
1
1,2
1, 2
1, 2
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
8
9DBV0841
REV C 081214