9DBV0841 Datasheet, PDF (6/16 Pages) Integrated Circuit Systems – HCSL compatible differential input

9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0841. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
1.8V Supply Voltage
VDDxx
Applies to VDD, VDDA and VDDIO
Input Voltage
V_IN
Input High Voltage, SMBus V_IHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Operation under these conditions is neither implied nor guaranteed.}
3 _{Not to exceed 2.5V.}
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
V_DD+0.5V
3.6V
150
125
UNITS
V
V
V
°C
°C
V
NOTES
1,2
1, 3
1
1
1
1
Electrical Characteristics–Clock Input Parameters
TA = T_COM or T_IND; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage - DIF_IN V_IHDIF
Differential inputs
(single-ended measurement)
Input Low Voltage - DIF_IN V_ILDIF
Differential inputs
(single-ended measurement)
Input Common Mode
Voltage - DIF_IN
V_COM
Common Mode Input Voltage
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
V_SWING
dv/dt
Peak to Peak value (V_IHDIF - V_ILDIF)
Measured differentially
Input Leakage Current
I_IN
V_IN = V_{DD ,} V_IN = GND
Input Duty Cycle
d_tin
Measurement from differential wavefrom
Input Jitter - Cycle to Cycle J_DIFIn
Differential Measurement
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Slew rate measured through +/-75mV window centered around differential zero}
600
800
V_SS - 300
300
300
0.4
-5
45
0
0
0.01
1150
mV
1
300
mV 1,3
725
mV
1
1450
mV
1
V/ns 1,2
5
uA
1
55
%
1
150
ps
1
3 _{The device can be driven from a single ended clock by driving the true clock and biasing the complement clock input to the VBIAS, where VBIAS}
is (V_IHHIGH - V_IHLOW)/2
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
6
9DBV0841
REV C 081214