9DBV0841 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – HCSL compatible differential input

9DBV0841
8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSADR_tri 1
36 DIF5#
^vHIBW_BYPM_LOBW# 2
35 DIF5
FB_DNC 3
34 vOE4#
FB_DNC# 4
33 DIF4#
VDDR1.8 5
32 DIF4
CLK_IN 6
CLK_IN# 7
9DBV0841
31 VDDIO
30 VDDA1.8
GNDR 8
29 GNDA
GNDDIG 9
28 vOE3#
SCLK_3.3 10
27 DIF3#
SDATA_3.3 11
26 DIF3
VDDDIG1.8 12
25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
Power Management Table
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
CKPWRGD_PD#
CLK_IN
SMBus
OEx bit
OEx# Pin
DIFx
PLL
True O/P Comp. O/P
0
X
X
X
Low
Low
Off
1
Running
0
X
Low
Low
On¹
1
Running
1
0
Running
Running
On¹
1
Running
1
1
Low
Low
On¹
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
Power Connections
Pin Number
VDD
VDDIO
5
12
20, 31, 38
30
13, 21, 31,
39, 47
GND
8
9
Description
Input
receiver
analog
Digital Power
22, 29, 40 DIF outputs
29
PLL Analog
Frequency Select Table
FSEL
Byte3 [4:3]
00 (Default)
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
IDT® 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
2
9DBV0841
REV C 081214