ICS8745BI Datasheet, PDF (7/20 Pages) Integrated Device Technology – 1:5 Differential-to-LVDS Zero Delay Clock Generator

ICS8745BI Data Sheet
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
AC Electrical Characteristics
Table 6. AC Characteristics, V_DD = V_DDO = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
f_MAX
t_PD
tsk(Ø)
Output Frequency
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
PLL_SEL = 0V, f ≤ 700MHz
PLL_SEL = 3.3V
tsk(o)
Output Skew; NOTE 3, 5
tjit(cc) Cycle-to-Cycle Jitter; NOTE 5, 6
tjit(θ)
Phase Jitter; NOTE 4, 5, 6
t_L
t_R / t_F
odc
PLL Lock Time
Output Rise/Fall Time; NOTE 7
Output Duty Cycle
20% to 80%
Minimum
2.9
-100
200
45
Typical
3.4
25
50
Maximum
700
4.0
150
40
30
±52
1
700
55
Units
MHz
ns
ps
ps
ps
ps
ms
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions..
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when
the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
ICS8745BYI REVISION D JUNE 11, 2009
7
©2009 Integrated Device Technology, Inc.