ICS8745BI Datasheet, PDF (1/20 Pages) Integrated Device Technology – 1:5 Differential-to-LVDS Zero Delay Clock Generator

1:5 Differential-to-LVDS Zero Delay
Clock Generator
ICS8745BI
DATA SHEET
General Description
The ICS8745BI is a highly versatile 1:5 LVDS Clock
ICS
Generator and a member of the HiPerClockS™ family
HiPerClockS™ _{of High Performance Clock Solutions from IDT. The}
ICS8745BI has a fully integrated PLL and can be
configured as zero delay buffer, multiplier or divider,
and has an output frequency range of 31.25MHz to 700MHz. The
Reference Divider, Feedback Divider and Output Divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the input
clock and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
• Five differential LVDS outputs designed to meet
or exceed the requirements of ANSI TIA/EIA-644
• Selectable differential clock inputs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 30ps (maximum)
• Output skew: 40ps (maximum)
• Static phase offset: 25ps ± 125ps
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
PLL_SEL ^Pullup
CLK0 ^Pulldown
nCLK0 ^Pullup
0
CLK1 ^Pulldown
nCLK1 ^Pullup
1
CLK_SEL ^Pulldown
FB_IN ^Pulldown
nFB_IN ^Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
SEL0 ^Pulldown
SEL1 ^Pulldown
SEL2 ^Pulldown
SEL3 ^Pulldown
MR ^Pulldown
ICS8745BYI REVISION D JUNE 11, 2009
Pin Assignment
Q0
nQ0
Q1
nQ1
0
32 31 30 29 28 27 26 25
Q2
SEL0 1
24 Q3
nQ2
1
SEL1 2
Q3
23 nQ3
nQ3
CLK0 3
22 VDDO
Q4
nCLK0 4
21 ^Q2
nQ4
CLK1 5
20 nQ2
nCLK1
CLK_SEL
MR
6
19
7
18
8
17
9 10 11 12 13 14 15 16
GND
Q1
nQ1
ICS8745BI
32-Lead LQFP 7mm x 7mm x 1.4mm
package body
Top View
1
©2009 Integrated Device Technology, Inc.