ICS8745BI Datasheet, PDF (10/20 Pages) Integrated Device Technology – 1:5 Differential-to-LVDS Zero Delay Clock Generator

ICS8745BI Data Sheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS8745BI provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V_DD, V_DDA and V_DDO should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V_DD pin and also shows that V_DDA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the V_DDA pin.
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
3.3V
V_DD
.01µF _10Ω
V_DDA
.01µF
10µF
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and V_DD = 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
Single Ended Clock Input
V_REF
C1
0.1u
VDD
R1
1K
CLKx
nCLKx
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
ICS8745BYI REVISION D JUNE 11, 2009
10
©2009 Integrated Device Technology, Inc.