ICS8745BI Datasheet, PDF (12/20 Pages) Integrated Device Technology – 1:5 Differential-to-LVDS Zero Delay Clock Generator

ICS8745BI Data Sheet
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
CLK/nCLK Input
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100Ω across. If they are left floating, we recommend that there
is no trace attached.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω differential
transmission line environment, LVDS drivers require a matched load
termination of 100Ω across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
3.3V
50Ω
LVDS Driver
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
R1
100Ω
3.3V
+
–
ICS8745BYI REVISION D JUNE 11, 2009
12
©2009 Integrated Device Technology, Inc.