ICS8745BI Datasheet, PDF (4/20 Pages) Integrated Device Technology – 1:5 Differential-to-LVDS Zero Delay Clock Generator

ICS8745BI Data Sheet
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Table 3B. PLL Bypass Function Table
Inputs
SEL3
0z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q[0:4], nQ[0:4]
÷4
÷4
÷4
÷8
÷8
÷8
÷16
÷16
÷32
÷64
÷2
÷2
÷4
÷1
÷2
÷1
ICS8745BYI REVISION D JUNE 11, 2009
4
©2009 Integrated Device Technology, Inc.