 English |
|
|
|
|
|
|
|
| ICS8745BI Datasheet, PDF (6/20 Pages) Integrated Device Technology – 1:5 Differential-to-LVDS Zero Delay Clock Generator | |||
| |||
| ◁ |
ICS8745BI Data Sheet
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
CLK0, CLK1,
FB_IN
VDD = VIN = 3.465V
IIH
Input High Current
nCLK0, nCLK1,
nFB_IN
VDD = VIN = 3.465V
IIL
VPP
VCMR
Input Low Current
CLK0, CLK1,
FB_IN
nCLK0, nCLK1,
nFB_IN
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
VDD = 3.465V,
VIN = 0V
VDD = 3.465V,
VIN = 0V
-5
-150
0.15
GND + 0.5
NOTE 1: VIL should not be less than -0.3V
NOTE 2: For single-ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V.
Typical
Maximum
150
5
1.3
VDD â 0.85
Units
µA
µA
µA
µA
V
V
Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VOD
âVOD
VOS
âVOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
320
1.05
Typical
440
0
1.2
Maximum
550
50
1.35
25
Units
mV
mV
V
mV
Table 5. Input Frequency Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
FIN
Input Frequency
CLK0/nCLK0,
CLK1/nCLK1
PLL_SEL = 1
PLL_SEL = 0
31.25
Typical
Maximum
700
700
Units
µA
V
ICS8745BYI REVISION D JUNE 11, 2009
6
©2009 Integrated Device Technology, Inc.
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese