ICS8745BI Datasheet, PDF (2/20 Pages) Integrated Device Technology – 1:5 Differential-to-LVDS Zero Delay Clock Generator

ICS8745BI Data Sheet
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 2,
12, 29
3
4
5
6
7
8
9, 32
10
11
13, 19, 25
14, 15
16, 22, 28
17, 18
20, 21
23, 24
26, 27
30
31
Name
SEL0, SEL1,
SEL2 SEL3
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V_DD
FBIN
FBIN
GND
nQ0/Q0
V_DDO
nQ1/Q1
nQ2/Q2
nQ3/Q3
nQ4/Q4
V_DDA
PLL_SEL
Type
Description
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Input
Input
Input
Input
Input
Input
Power
Input
Input
Power
Output
Power
Output
Output
Output
Output
Power
Input
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Clock select input. When HIGH, selects CLK1,nCLK1. When LOW, selects CLK0,
nCLK0. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Core supply pins.
Inverting differential feedback input to phase detector for regenerating clocks with
“Zero Delay.”
Non-inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
Power supply ground.
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Analog supply pin.
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
ICS8745BYI REVISION D JUNE 11, 2009
2
©2009 Integrated Device Technology, Inc.