841S104EGILF Datasheet, PDF (7/22 Pages) Integrated Device Technology – Crystal-to-HCSL 100MHz PCI ExpressTM Clock Synthesizer

ICS841S104I Data Sheet
CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS^TM CLOCK SYNTHESIZER
Table 4B. LVCMOS/LVTTL DC Characteristics, V_DD = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
V_IH
Input High Voltage
V_IL
Input Low Voltage
I_IH
Input High Current SDATA, SCLK
I_IL
Input Low Current SDATA, SCLK
V_DD = V_IN = 3.465V
V_DD = 3.465V, V_IN = 0V
2.2
-0.3
-150
Typical
Maximum
V_DD + 0.3
0.8
10
Units
V
V
µA
µA
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
25
50
7
Units
MHz
Ω
pF
AC Electrical Characteristics
Table 6A. PCI Express Jitter Specifications, V_DD = 3.3V±5%, T_A = -40°C to 85°C
Parameter
t_j
(PCIe Gen 1)
Symbol
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
t_{REFCLK_HF_RMS Phase Jitter RMS;}
(PCIe Gen 2) ^{NOTE 2, 4}
t_{REFCLK_LF_RMS Phase Jitter RMS;}
(PCIe Gen 2) ^{NOTE 2, 4}
t_{REFCLK_RMS}
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 3, 4
Test Conditions
ƒ= 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ= 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ= 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
ƒ= 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum
Typical
13.8
1.34
0.18
0.28
Maximum
21
3.03
0.3
0.71
PCIe Industry
Specification
86
3.1
3.0
0.8
Units
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10⁶ clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_{REFCLK_HF_RMS}
(High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS} (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
ICS841S104EGI REVISION A JUNE 18, 2010
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©2010 Integrated Device Technology, Inc.