841S104EGILF Datasheet, PDF (16/22 Pages) Integrated Device Technology – Crystal-to-HCSL 100MHz PCI ExpressTM Clock Synthesizer

ICS841S104I Data Sheet
CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS^TM CLOCK SYNTHESIZER
Schematic Layout
Figure 5 shows an example of ICS841S104I application schematic.
In this example, the device is operated at V_DD = 3.3V. The 18pF
parallel resonant 25MHz crystal is used. The C1 =18pF and C2 =
33pF are recommended for frequency accuracy. For different board
layouts, the C1 and C2 may be slightly adjusted for optimizing
frequency accuracy. Two examples of HCSL termination are shown
in this schematic. The decoupling capacitors should be located as
close as possible to the power pin.
VDD
IREF
R13
475 Ohm
SRCT1
SRCC1
VDD
U1
R5 33
R7 33
Zo = 50
TL3
Zo = 50
TL5
R8
R9
50
50
VDD=3.3V
+
-
Recommended for PCI
Express Add-In Card
HCSL Termination
VDD
R3
10
VDDA
C3
10uF
VDD
C4
0.01u
VDD
25MHz
C2
X1 _{1 8 p F}
33pF
R6 R7
SP SP
C1
18pF
J1
R8
0
5 SDA
4
3
2
R9
0
1 SCL
SRCT4
Zo = 50
+
TL6
SRCC4
Zo = 50
-
TL7
VDD
R11 R12
50
50
Recommended for PCI
Express Point-to-Point
Connection
VDD
(U1-4)
(U1-10)
VDD
(U1-17)
(U1-22)
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
Figure 5. ICS841S104I Application Schematic.
ICS841S104EGI REVISION A JUNE 18, 2010
16
©2010 Integrated Device Technology, Inc.