841S104EGILF Datasheet, PDF (12/22 Pages) Integrated Device Technology – Crystal-to-HCSL 100MHz PCI ExpressTM Clock Synthesizer

ICS841S104I Data Sheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS841S104I provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V_DD and V_DDA should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V_DD pin and also shows that V_DDA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the V_DDA pin.
CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS^TM CLOCK SYNTHESIZER
3.3V
V_DD
.01µF _10Ω
V_DDA
.01µF
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
ICS841S104EGI REVISION A JUNE 18, 2010
12
©2010 Integrated Device Technology, Inc.