841S104EGILF Datasheet, PDF(5/22 Page) Integrated Device Technology – Crystal-to-HCSL 100MHz PCI ExpressTM Clock Synthesizer

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841S104EGILF Datasheet, PDF (5/22 Pages) Integrated Device Technology – Crystal-to-HCSL 100MHz PCI ExpressTM Clock Synthesizer

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ICS841S104I Data Sheet

CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Control Registers

Table 3D. Byte 0: Control Register 0

Bit

@Pup

Name Description

Reserved Reserved

SRC[T/C]4 Output Enable

SRC[T/C]4 0 = Disable (Hi-Z)

1 = Enable

SRC[T/C]3 Output Enable

SRC[T/C]3 0 = Disable (Hi-Z)

1 = Enable

SRC[T/C]2 Output Enable

SRC[T/C]2 0 = Disable (Hi-Z)

1 = Enable

SRC[T/C]1 Output Enable

SRC[T/C]1 0 = Disable (Hi-Z)

1 = Enable

Reserved Reserved

NOTE: Pup denotes Power-up.

Table 3E. Byte 1: Control Register 1

Bit

@Pup

Name

Description

Reserved

Table 3F. Byte 2: Control Register 2

Bit

@Pup

Name Description

SRCT/C

Spread Spectrum Selection

0 = -0.35%, 1 = - 0.5%

Reserved Reserved

SRC Spread Spectrum

SRC

Enable

0 = Spread Off,

1 = Spread On

Reserved Reserved

Table 3G. Byte 3:Control Register 3

Bit

@Pup

Name

Description

Reserved

Table 3H. Byte 4: Control Register 4

Bit

@Pup

Name

Description

Reserved

Table 3I. Byte 5: Control Register 5

Bit

@Pup

Name

Description

Reserved

ICS841S104EGI REVISION A JUNE 18, 2010

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