ICS845252I Datasheet, PDF (6/17 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-CML Clock Generator

ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
AC Characteristics
Table 6A. AC Characteristics, V_DD = 3.3V±5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
FBSEL = 0, FSEL[1:0] = 00
FBSEL = 0, FSEL[1:0] = 01
FBSEL = 0, FSEL[1:0] = 10
f_OUT
Output Frequency; NOTE 1
FBSEL = 0, FSEL[1:0] = 11
FBSEL = 1, FSEL[1:0] = 00
FBSEL = 1, FSEL[1:0] = 01
FBSEL = 1, FSEL[1:0] = 10
FBSEL = 1, FSEL[1:0] = 11
tsk(o) Output Skew; NOTE 1, 2, 3
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 4
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
FSEL = 0, 125MHz,
Integration Range: 1.875MHz – 20MHz
FSEL = 0, 156.25MHz,
Integration Range: 1.875MHz – 20MHz
20% to 80%
FBSEL[1:0] ≠ 10
FBSEL[1:0] = 10
Minimum
Typical
312.5
156.25
125
62.5
250
125
100
50
400
Maximum
60
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
fs
408
fs
300
850
ps
48
52
%
46
54
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: f_REF = 25 MHz.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Please refer to the phase noise plots.
Table 6B. AC Characteristics, V_DD = 2.5V±5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
FBSEL = 0, FSEL[1:0] = 00
FBSEL = 0, FSEL[1:0] = 01
FBSEL = 0, FSEL[1:0] = 10
f_OUT
Output Frequency; NOTE 1
FBSEL = 0, FSEL[1:0] = 11
FBSEL = 1, FSEL[1:0] = 00
FBSEL = 1, FSEL[1:0] = 01
FBSEL = 1, FSEL[1:0] = 10
FBSEL = 1, FSEL[1:0] = 11
tsk(o) Output Skew; NOTE 1, 2, 3
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 4
FSEL = 0, 125MHz,
Integration Range: 1.875MHz – 20MHz
FSEL = 0, 156.25MHz,
Integration Range: 1.875MHz – 20MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
FBSEL[1:0] ≠ 10
FBSEL[1:0] = 10
For NOTES see Table 6A above.
ICS845252AKI REVISION A SEPTEMBER 30, 2009
6
Minimum
Typical
312.5
156.25
125
62.5
250
125
100
50
406
Maximum
60
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
fs
441
fs
300
850
ps
48
52
%
46
54
%
©2009 Integrated Device Technology, Inc.