ICS845252I Datasheet, PDF (3/17 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-CML Clock Generator

ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Function Tables
Table 3A. PLL Reference Clock Select Function Table
Input
REF_SEL
Operation
0 (default)
The crystal interface is the selected.
1
The REF_CLK input is the selected.
NOTE: REF_SEL is an asynchronous control.
Table 3B. PLL Feedback Select Function Table
Input
FBSEL
Operation
0 (default)
1
f_VCO = f_REF * 25
f_VCO = f_REF * 20
NOTE: FBSEL is an asynchronous control.
Table 3C. Output Divider Select Function Table
Input
FSEL1
FSEL0
Operation
Output Frequency f_OUT with f_REF = 25MHz
FBSEL = 0
FBSEL = 1
0 (default)
0
1
1
0 (default)
1
0
1
f_OUT = f_VCO ÷ 2
f_OUT = f_VCO ÷ 4
f_OUT = f_VCO ÷ 5
f_OUT = f_VCO ÷ 10
312.5MHz
156.25MHz
125MHz
62.5MHz
250MHz
125MHz
100MHz
50MHz
NOTE: FSEL[1:0] are asynchronous controls.
Table 3D. PLL nBYPASS Function Table
Input
nBYPASS
Operation
0
PLL is bypassed. The reference frequency f_REF is divided by the selected
output divider. AC specifications do not apply in PLL bypass mode.
1 (default)
PLL is enabled. The reference frequency f_REF is multiplied by the selected
feedback divider and then divided by the selected output divider.
NOTE: nBYPASS is an asynchronous control.
Table 3E. Output Enable Function Table
Input
nOE
Operation
0 (default)
Outputs enabled.
1
Outputs disabled (high-impedance).
NOTE: nOE is an asynchronous control.
ICS845252AKI REVISION A SEPTEMBER 30, 2009
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©2009 Integrated Device Technology, Inc.