ICS845252I Datasheet, PDF (15/17 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-CML Clock Generator

ICS845252I Data Sheet
Reliability Information
Table 8. θ_JA vs. Air Flow Table for a 32 VFQFN
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Transistor Count
The transistor count for the ICS845252I is: 3064
θ_JA vs. Air Flow
0
43.4°C/W
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
1
37.9°C/W
2.5
34.0°C/W
Package Outline and Package Dimensions
Package Outline - K Suffix for VFQFN Packages
Ind exArea
N
To p View
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
S eating Plan e
A1
A_An_nv_vi_il_l
Si_Sn_ig_ngu_ula_lati_to_ion_n
or
Sa^Ow^Rn
Singulation
A3 ^L
E 2 _E2
2
(N -1)x e
(R ef.)
N
A
0. 08 C
e
(Ref.)
N &N
Odd
C
D2
2
D2
(Ref.)
N &N
Even
e (Ty p.)
2 _{If N & N}
1 ^{are Even}
2
(N -1)x e
(Re f.)
b
Th er mal
Ba se
Table 9. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
N_D & N_E
D&E
8
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
ICS845252AKI REVISION A SEPTEMBER 30, 2009
15
©2009 Integrated Device Technology, Inc.