ICS845252I Datasheet, PDF (10/17 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-CML Clock Generator

ICS845252I Data Sheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS845252I provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V_DD and V_DDA should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V_DD pin and also shows that V_DDA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the V_DDA pin.
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
3.3V or 2.5V
VDD
.01µF _10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
Outputs:
CML Outputs
All unused CML outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
REF_CLK Input
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to ground.
ICS845252AKI REVISION A SEPTEMBER 30, 2009
10
©2009 Integrated Device Technology, Inc.