ICS845252I Datasheet, PDF (13/17 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-CML Clock Generator

ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS845252I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS845252I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{DD_MAX} * (I_DD + I_DDA) = 3.465V * (88mA + 12mA) = 346.5mW
• Power (outputs)_MAX = 35.76mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 35.76mW = 71.52mW
Total Power__MAX (3.465V, with all outputs switching) = 346.5mW + 71.52mW = 418.02mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 43.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.418W * 43.4°C/W = 103°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θ_JA for 32 Lead VFQFN, Forced Convection
θ_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
43.4°C/W
1
37.9°C/W
2.5
34.0°C/W
ICS845252AKI REVISION A SEPTEMBER 30, 2009
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©2009 Integrated Device Technology, Inc.