ICS845252I Datasheet, PDF (14/17 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-CML Clock Generator

ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the CML driver output pair. The CML output circuit and termination are
shown in Figure 5.
VDD
RL1
50
Q
nQ
Q1
Q2
I_load
RL2
50
V_output
IC
Figure 5. CML Driver (without built-in 50Ω pullup) Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations:
Power dissipation when the output driver is logic LOW:
Pd_L = I Load * V Output
= (V_{OUT_MAX} /R_L) * (V_{DD_MAX} – V_{OUT_MAX})
= (600mV/50Ω) * (3.465V – 600mV)
= 34.38mW
Power dissipation when the output driver is logic HIGH:
Pd_H = I Load * V Output
= (0.02V/50Ω) * (3.465V – 0.02V)
= 1.38mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 35.76mW
ICS845252AKI REVISION A SEPTEMBER 30, 2009
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©2009 Integrated Device Technology, Inc.