ICS845252I Datasheet, PDF (2/17 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-CML Clock Generator

ICS845252I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 2
3, 18
4
5, 6, 7, 8, 9, 16,
17, 19, 23, 24,
25, 30, 31, 32
10
11
12
13, 29
14,
15
Name
nQ0, Q0
V_DD
nOE
nc
V_DDA
nBYPASS
REF_CLK
GND
XTAL_OUT,
XTAL_IN
Type
Output
Power
Input
Pulldown
Description
Differential clock output pair. CML interface levels.
Core supply pins.
Output enable pin. See Table 3E for function.
LVCMOS/LVTTL interface levels.
Unused
Do not connect.
Power
Input
Input
Power
Input
Pullup
Pulldown
Analog supply pin.
PLL bypass pin. See Table 3D for function.
LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
20, 21
FSEL0, FSEL1 Input
Pulldown ^{Output frequency divider select enable pins. See Table 3C for function.}
LVCMOS/LVTTL interface levels.
22
REF_SEL
Input
Pulldown ^{PLL reference clock select pin. See Table 3A for function.}
LVCMOS/LVTTL interface levels.
26
27, 28
FBSEL
nQ1, Q1
Input
Output
Pulldown
PLL feedback divider select pin. See Table 3B for function.
LVCMOS/LVTTL interface levels.
Differential clock output pair. CML interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
R_PULLDOWN
R_PULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
ICS845252AKI REVISION A SEPTEMBER 30, 2009
2
©2009 Integrated Device Technology, Inc.