ICS8430002 Datasheet, PDF (6/27 Pages) Integrated Device Technology – High-Performance Fractional-N Frequency Synthesizer

ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Number
27
28
29
30
33,
34
37
38
39
40
41, 42, 43,
44, 45
46
Name
S_DATA
S_LOAD
V_CCA
SEL
XTAL_IN
XTAL_OUT
PCLK
nPCLK
nP_LOAD
VCO_SEL
M0, M1, M2,
M3, M4
M5
Type
Input Pulldown
Input
Power
Pulldown
Input Pulldown
Description
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Selects between the crystal oscillator or the PCLK/nPCLK inputs as the PLL
reference source. Selects XTAL inputs when LOW. Selects PCLK/nPCLK when
HIGH. LVCMOS/LVTTL interface levels.
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Input
Input
Input
Input
Input
Input
Pulldown
Pullup/
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Non-inverting differential clock input.
Inverting differential clock input. V_CC/2 default when left floating.
Parallel load input. Determines when data present at M5:M0 is loaded into M
divider, and when data present at NA2:NA0 and NB2:NB0 is loaded into the N
output divider value. LVCMOS/LVTTL interface levels.
Determines whether the synthesizer is in PLL or Bypass mode. LVCMOS/LVTTL
interface levels.
M divider integer inputs. The fractional portion of M divider can only be
programmed by serial interface. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
R_OUT
Output Impedance REF_OUT
Test Conditions
Minimum
Typical
4
51
51
7
Maximum
Units
pF
kΩ
kΩ
Ω
ICS8430002AY REVISION C NOVEMBER 12, 2009
6
©2009 Integrated Device Technology, Inc.