ICS8430002 Datasheet, PDF (17/27 Pages) Integrated Device Technology – High-Performance Fractional-N Frequency Synthesizer

ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V_SWING and V_OH must meet the V_PP and
V_CMR input requirements. Figures 6A to 6E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK
LVPECL
Input
LVPECL
Input
Figure 6A. PCLK/nPCLK Input
Driven by an Open Collector CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
R4
125
125
3.3V
PCLK
nPCLK
LVPECL
R1
R2
84
84
Input
Figure 6B. PCLK/nPCLK Input
Driven by a Built-In Pullup CML Driver
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
100 - 200
R6
100 - 200
3.3V
R3
R4
84
84
C1
C2
R1
R2
125 125
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 6C. PCLK/nPCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
LVPECL
Input
Figure 6E. PCLK/nPCLK Input
Driven by an SSTL Driver
Figure 6D. PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
ICS8430002AY REVISION C NOVEMBER 12, 2009
17
©2009 Integrated Device Technology, Inc.