ICS8430002 Datasheet, PDF (5/27 Pages) Integrated Device Technology – High-Performance Fractional-N Frequency Synthesizer

ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
The internal registers T0 and T1 determine the state of the TEST
output as follows:
T1
T0 TEST Output
0
0 LOW
0
1 S_DATA, Shift Register Output
1
0 Reserved
1
1 Reserved
The function of the DS1, and DS0 bits is as follows:
DS1 DS0 Function
0
0 Integer Mode Only
1
1 Fractional Mode Only
0
1 Do Not Use
1
0 Do Not Use
Table 1. Pin Descriptions
Number
1, 47, 48
2, 3
4
5
Name
P2, P0, P1
NB0, NB1
NB2
OE_REF
6
OEA
7
8, 14
9, 10
11
12, 24
13
15, 16
17
18, 19
20
21
22
23, 31, 32,
35, 36
OEB
V_CC
NA0, NA1
NA2
V_EE
TEST
FOUTA,
nFOUTA
V_{CCO_A}
FOUTB,
nFOUTB
V_{CCO_B}
REF_OUT
V_{CCO_REF}
nc
25
MR
26
S_CLOCK
continued on next page.
Type
Input Pulldown
Input
Pullup
Input Pulldown
Input Pulldown
Input
Pullup
Input
Pullup
Power
Input
Input
Power
Output
Pullup
Pulldown
Description
Pre-divider control input pins. See table 3C. LVCMOS/LVTTL interface levels.
Determines output divider value as defined in Table 3D, Function Table.
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of REF_OUT output. When HIGH,
the output is active. When LOW, the output is high-impedance. LVCMOS/LVTTL
interface levels.
Output enable. Controls enabling and disabling of FOUTA, nFOUTA outputs.
When HIGH, the outputs are active. When LOW, the true output is low and the
compliment output is high. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB, nFOUTB outputs.
When HIGH, the outputs are active. When LOW, the true output is low and the
compliment output is high. LVCMOS/LVTTL interface levels.
Core supply pins.
Determines output divider value as defined in Table 3D, Function Table.
LVCMOS/LVTTL interface levels.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Output
Differential output pair for the synthesizer. LVPECL interface levels.
Power
Output supply pin for FOUTA/nFOUTA LVPECL outputs.
Output
Differential output pair for the synthesizer. LVPECL interface levels.
Power
Output
Power
Output supply pin for FOUTB/nFOUTB LVPECL outputs.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_OUT.
Unused
No internal connection.
Input
Input
Pulldown
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to go
high. When Logic LOW, the internal dividers and the outputs are enabled.
Assertion of MR does not affect loaded M, N, and T values.
LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on the rising
edge of S_CLOCK. LVCMOS/LVTTL interface levels.
ICS8430002AY REVISION C NOVEMBER 12, 2009
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©2009 Integrated Device Technology, Inc.