ICS8430002 Datasheet, PDF (4/27 Pages) Integrated Device Technology – High-Performance Fractional-N Frequency Synthesizer

ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Assuming a 25MHz reference frequency and a VCO frequency of
637.5MHz (which, with an output divider of 6 would give an output
frequency of 106.25MHz, a common Fibre channel reference
frequency), requires an M setting of 25.5 (the integer portion being
25 and the fractional portion being 2048/4096). If you decrease the
fractional portion of the M divider by one bit (from 2048 to 2047), the
frequency change in ppm is calculated by:
stepsize = ⁽_{---2---5---.-5-----}^–_{-----2---5---.-4---9---9---7---5---5---8---5---9---3---7---5---}⁾_- × 1×10⁶ppm
25.5
Which, for these conditions, is a step size of 9.6 ppm.
The ICS8430002 supports either serial or parallel programming
modes to program the P pre-divider, M feedback divider and N output
divider, however the parallel interface can only program the integer
portion of the feedback divider. The fractional portion of the feedback
divider must be programmed serially. Figure 1 shows the timing
diagram for each mode. In parallel mode, the nP_LOAD input is
initially LOW. The data on the M, NA, and NB inputs are passed
directly to the M divider and both N output dividers. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M and N dividers remain loaded until the next LOW transition
on nP_LOAD or until a serial event occurs. As a result, the M and Nx
bits can be hardwired to set the M divider and Nx output divider to a
specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode.
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the P pre-divider, M divider and Nx output divider when
S_LOAD transitions from LOW-to-HIGH. The P pre-divider, M divider
and Nx output divider values are latched on the HIGH-to-LOW
transition of S_LOAD. The serial mode can be used to program the
P, M and Nx bits and test bits T1 and T0. The data bits are clocked in
the following order as in the table below.
T1
T0
NB2
NB1
NB0
NA2
NA1
NA0
P2
P1
P0
DS1
DS0 _{. . .}
M_FRAC11 M_FRAC10 M_FRAC9 M_FRAC8 M_FRAC7 M_FRAC6 M_FRAC5 M_FRAC4 M_FRAC3 M_FRAC2 M_FRAC1 M_FRAC0 _{. . .}
M_INT5
M_INT4
M_INT3
M_INT2
M_INT1
M_INT0
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
tt
SH
nP_LOAD
t
PARALLEL LOADING
S
M[5:0], NX[2:0], P[2:0]
M, N, P
nP_LOAD
tt
SH
S_LOAD
Time
Figure 1. Parallel & Serial Load Operations
ICS8430002AY REVISION C NOVEMBER 12, 2009
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©2009 Integrated Device Technology, Inc.