ICS8430002 Datasheet, PDF (18/27 Pages) Integrated Device Technology – High-Performance Fractional-N Frequency Synthesizer

ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
PCLK/nPCLK Inputs
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
Outputs:
TEST Output
The unused TEST output can be left floating. There should be no
trace attached.
LVCMOS Output
All unused LVCMOS output can be left floating. There should be no
trace attached.
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 7A and 7B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
Z_o = 50Ω
3.3V
+
LVPECL
Z_o = 50Ω
R1
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
* Z_o
_
Input
R2
50Ω
V_CC - 2V
RTT
Figure 7A. 3.3V LVPECL Output Termination
3.3V
LVPECL
3.3V
R3
R4
125Ω
125Ω
3.3V
Z_o = 50Ω
+
Z_o = 50Ω
R1
84Ω
_
R2
84Ω
Input
Figure 7B. 3.3V LVPECL Output Termination
ICS8430002AY REVISION C NOVEMBER 12, 2009
18
©2009 Integrated Device Technology, Inc.