70V28L20PFGI Datasheet, PDF (6/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM

IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1 and 2
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Industrial and Commercial Temperature Ranges
3.3V
3.3V
DATAOUT
BUSY
INT
435Ω
590Ω
30pF
DATAOUT
435Ω
590Ω
5pF*
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Figure 1. AC Output Load
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Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
Waveform of Read Cycles⁽⁵⁾
tRC
ADDR
CE⁽⁶⁾
tAA ⁽⁴⁾
tACE ⁽⁴⁾
tAOE ⁽⁴⁾
OE
UB, LB
tABE ⁽⁴⁾
R/W
DATAOUT
BUSYOUT
tLZ ⁽¹⁾
(4)
VALID DATA
tBDD ^(3,4)
tOH
tHZ ⁽²⁾
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Timing of Power-Up Power-Down
CE⁽⁶⁾
ICC
ISB
tPU
50%
tPD
50%
.
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NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Truth Table I - Chip Enable.
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