70V28L20PFGI Datasheet, PDF (13/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM

IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Waveform of Interrupt Timing^(1,5)
Industrial and Commercial Temperature Ranges
tWC
ADDR"A"
CE"A"
INTERRUPT SET ADDRESS ⁽²⁾
tAS⁽³⁾
tWR ⁽⁴⁾
R/W"A"
INT"B"
tINS ⁽³⁾
ADDR"B"
CE"B"
tRC
INTERRUPT CLEAR ADDRESS ⁽²⁾
tAS⁽³⁾
OE"B"
INT"B"
tINR ⁽³⁾
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Truth Table I - Chip Enable.
4849 drw 15
4849 drw 16
Truth Table IV — Interrupt Flag^(1,4,5)
Left Port
R/WL
CEL
OEL
A15L-A0L
INTL
R/WR
CER
L
L
X
FFFF
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L⁽³⁾
L
L
X
L
L
FFFE
H⁽²⁾
X
X
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Truth Table I - Chip Enable.
Right Port
OER
A15R-A0R
X
X
L
FFFF
X
FFFE
X
X
13
INTR
Function
L⁽²⁾ Set Right INTR Flag
H⁽³⁾ Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
4849 tbl 16