70V28L20PFGI Datasheet, PDF (12/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM

IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)^(1,3)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
CE"B"
BUSY"B"
tAPS ⁽²⁾
tBAC
tBDC
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Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)⁽¹⁾
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
tAPS ⁽²⁾
MATCHING ADDRESS "N"
tBAA
tBDA
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Truth Table I - Chip Enable.
,
4849 drw 14
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70V28L15
Com'l Only
Symbol
INTERRUPT TIMING
tAS
Address Set-up Time
tWR
Write Recovery Time
tINS
Interrupt Set Time
tINR
Interrupt Reset Time
Parameter
Min. Max.
0
____
0
____
____
15
____
15
70V28L20
Com'l
& Ind
Min. Max. Unit
0
____
ns
0
____
ns
____
20
ns
____
20
ns
4849 tbl 15
12