70V28L20PFGI Datasheet, PDF (5/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM

IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V28L
Symbol
Parameter
Test Conditions
Min.
Max. Unit
|ILI|
Input Leakage Current⁽¹⁾
VCC = 3.6V, VIN = 0V to VCC
___
5
µA
|ILO|
Output Leakage Current
CE⁽²⁾ = VIH, VOUT = 0V to VCC
___
5
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
V
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Truth Table I - Chip Enable.
4849 tbl 09
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range⁽⁵⁾ (VCC = 3.3V ± 0.3V)
70V28L15
Com'l Only
70V28L20
Com'l
& Ind
Symbol
Parameter
Test Condition
Version Typ.⁽¹⁾ Max. Typ.⁽¹⁾ Max. Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX⁽²⁾
COM'L L 145 235 135 205 mA
IND
L
___
___
135 220
ISB1
Standby Current
(Both Ports - TTL Level
Inputs)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX⁽²⁾
COM'L L 40 70 35 55 mA
IND
L
___
___
35
65
ISB2
Standby Current
(One Port - TTL Level
Inputs)
CE"A" = VIL and CE"B" = VIH⁽⁴⁾
Active Port Outputs Disabled,
f=fMAX⁽²⁾, SEMR = SEML = VIH
COM'L L 100 155 90 140 mA
IND
L
___
___
90 150
ISB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CEL and CER > VCC - 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V, f = 0⁽³⁾
SEMR = SEML > VCC - 0.2V
COM'L L 0.2 3.0 0.2 3.0 mA
IND
L
___
___
0.2 3.0
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VCC - 0.2V⁽⁴⁾,
SEMR = SEML > VCC - 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V,
Active Port Outputs Disabled , f = fMAX⁽²⁾
COM'L L 95 150 90 135 mA
IND
L
___
___
90 145
NOTES:
4849 tbl 10
1. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND
to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Truth Table I - Chip Enable.
5