70V28L20PFGI Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V
64K x 16 DUAL-PORT
STATIC RAM
IDT70V28L
Features
◆ _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed access}
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
◆ _{Low-power operation}
– IDT70V28L
Active: 440mW (typ.)
Standby: 660µW (typ.)
◆ _{Dual chip enables allow for depth expansion without}
external logic
◆ _{IDT70V28 easily expands data bus width to 32 bits or}
more using the Master/Slave select when cascading more
than one device
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
◆ _{M/S = VIH for BUSY output flag on Master,}
M/S = VIL for BUSY input on Slave
◆ _{Busy and Interrupt Flags}
◆ _{On-chip port arbitration logic}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{Separate upper-byte and lower-byte controls for multi-}
plexed bus and bus matching compatibility
◆ _{LVTTL-compatible, single 3.3V (±0.3V) power supply}
◆ _{Available in a 100-pin TQFP}
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
◆ _{Green parts available, see ordering information}
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O ^8-15L
I/O 0-7L
BUSYL^(1,2)
I/O
Control
I/O
Control
A15L
A0L
Address
Decoder
16
CE0L
CE1L
OEL
R/WL
64Kx16
MEMORY
ARRAY
70V28
16
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INT
(2)
L
NOTES:
M/S⁽¹⁾
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2008 Integrated Device Technology, Inc.
Address
Decoder
I/O8-15R
I/O0-7R
BUSYR^(1,2)
A15R
A0R
CE0R
CE1R
OER
R/WR
SEMR
INTR ⁽²⁾
4849 drw 01
OCTOBER 2008
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