70V28L20PFGI Datasheet, PDF (10/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM

IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol
BUSY TIMING (M/S=VIH)
Parameter
70V28L15
70V28L20
Com'l Only
Com'l
& Ind
Unit
Min. Max. Min. Max.
tBAA
BUSY Access Time from Address Match
____
15
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
20
ns
tBAC
BUSY Access Time from Chip Enable Low
____
15
____
20
ns
tBDC
BUSY Access Time from Chip Enable High
____
15
____
17
ns
tAPS
Arbitration Priority Set-up Time⁽²⁾
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data⁽³⁾
tWH
Write Hold After BUSY⁽⁵⁾
BUSY TIMING (M/S=VIL)
____
15
____
17
ns
12
____
15
____
ns
tWB
BUSY Input to Write⁽⁴⁾
0
____
0
____
ns
tWH
Write Hold After BUSY⁽⁵⁾
12
____
15
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay⁽¹⁾
____
30
____
45
ns
tDDD
Write Data Valid to Read Data Delay⁽¹⁾
____
25
____
30
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
4849 tbl 14
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