70V28L20PFGI Datasheet, PDF (4/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM

IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I – Chip Enable^(1,2)
CE
CE0
CE 1
Mode
VIL
V IH
Port Selected (TTL Active)
L
< 0.2V
>VCC -0.2V
Port Selected (CMOS Active)
VIH
X
Port Deselected (TTL Inactive)
H
X
>VCC -0.2V
VIL
Port Deselected (TTL Inactive)
X⁽³⁾
Port Deselected (CMOS Inactive)
X⁽³⁾
<0.2V
Port Deselected (CMOS Inactive)
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only.
2. 'H' = VIH and 'L' = VIL.
3. CMOS standby requires 'X' to be either < 0.2V or >VCC-0.2V.
4849tbl 06
Truth Table II – Non-Contention Read/Write Control
Inputs⁽¹⁾
Outputs
CE⁽²⁾
R/W
OE
UB
LB
SEM
I/O8-15
I/O0-7
Mode
H
X
X
X
X
H
High-Z
High-Z Deselected: Power-Down
X
X
X
H
H
H
High-Z
High-Z Both Bytes Deselected
L
L
X
L
H
H
DATAIN
High-Z Write to Upper Byte Only
L
L
X
H
L
H
High-Z DATAIN Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN Write to Both Bytes
L
H
L
L
H
H
DATAOUT High-Z Read Upper Byte Only
L
H
L
H
L
H
High-Z DATAOUT Read Lower Byte Only
L
H
L
L
L
H
DATAOUT DATAOUT Read Both Bytes
X
X
H
X
X
X
High-Z
High-Z Outputs Disabled
NOTES:
1. A0L — A15L ≠ A0R — A15R
2. Refer to Truth Table I - Chip Enable.
4849 tbl 07
Truth Table III – Semaphore Read/Write Control⁽¹⁾
Inputs⁽¹⁾
Outputs
CE⁽²⁾
R/W
OE
UB
LB
SEM
I/O8-15
I/O0-7
Mode
H
H
L
X
X
L
DATAOUT DATAOUT Read Data in Semaphore Flag
X
H
L
H
H
L
DATAOUT DATAOUT Read Data in Semaphore Flag
H
↑
X
X
X
L
DATAIN DATAIN Write I/O0 into Semaphore Flag
X
↑
X
H
H
L
DATAIN DATAIN Write I/O0 into Semaphore Flag
L
X
X
L
X
L
______
______
Not Allowed
L
X
X
X
L
L
______
______
Not Allowed
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O15). These eight semaphore flags are addressed by A0-A2.
2. Refer toTruth Table I - Chip Enable.
4
4849 tbl 08