TSI350 Datasheet, PDF (58/163 Pages) Integrated Device Technology – This chapter discusses the following

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4.3
4.3.1
4. Transaction Ordering > General Ordering Guidelines
Tsi350 does not combine or merge write transactions:
• Tsi350 does not combine separate write transactions into a single write transaction – this
optimization is best implemented in the originating master.
• Tsi350 does not merge bytes on separate masked write transactions to the same Dword address –
this optimization is also best implemented in the originating master.
• Tsi350 does not collapse sequential write transactions to the same address into a single write
transaction – the PCI Local Bus Specification does not permit this combining of transactions.
General Ordering Guidelines
Independent transactions on the primary and secondary buses have a relationship only when those
transactions cross Tsi350.
The following general ordering guidelines govern transactions crossing Tsi350:
• The ordering relationship of a transaction with respect to other transactions is determined when the
transaction completes, that is, when a transaction ends with a termination other than target retry.
• Requests terminated with target retry can be accepted and completed in any order with respect to
other transactions that have been terminated with target retry. If the order of completion of delayed
requests is important, the initiator should not start a second delayed transaction until the first one
has been completed. If more than one delayed transaction is initiated, the initiator should repeat all
the delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction
cannot be contingent on completion of another delayed transaction; otherwise, a deadlock can
occur.
• Write transactions flowing in one direction have no ordering requirements with respect to write
transactions flowing in the other direction. Tsi350 can accept posted write transactions on both
interfaces at the same time, as well as initiate posted write transactions on both interfaces at the
same time.
• The acceptance of a posted memory write transaction as a target can never be contingent on the
completion of a non-locked, non-posted transaction as a master. This is true of Tsi350 and must be
true of other bus agents; otherwise, a deadlock can occur.
• Tsi350 accepts posted write transactions, regardless of the state of completion of any delayed
transactions being forwarded across Tsi350.
Ordering Rules
Table 9 shows the ordering relationships of all the transactions and refers by number to the ordering
rules that follow.
The superscript accompanying some of the table entries refers to any applicable ordering
rule listed in this section. Many entries are not governed by these ordering rules; therefore,
the implementation can choose whether the transactions pass each other.
Tsi350 User Manual
January 10, 2014
Integrated Device Technology
www.idt.com