TSI350 Datasheet, PDF (137/163 Pages) Integrated Device Technology – This chapter discusses the following

15. Registers > PCI-to-PCI Bridge Standard Configuration Registers
137
Bit
Name
Type
Description
Reset
value
19
VGA enable
R/W
Modifies Tsi350’s response to VGA compatible
0
addresses.
0 = VGA transactions are ignored on the primary bus
unless they fall within the I/O base and limit address
registers and the ISA mode is 0.
1 = Tsi350 positively decodes and forwards the
following transactions downstream, regardless of the
values of the I/O base and limit registers, ISA mode
bit, or VGA snoop bit:
Memory transactions addressing
0x000A0000–0x000BFFFFh
I/O transactions addressing:
• P_AD[9:0] = 3B0h–3BBh and 3C0h–3DFh
• P_AD[15:10] are not decoded.
• P_AD[31:16] = 0000h.
I/O and memory space enable bits must be set in the
command register.
The transactions listed here are ignored by Tsi350 on
the secondary bus.
Reset value: 0.
20
Reserved
R
Reserved. Returns 0 when read.
0
21
Master abort mode
R/W
Controls Tsi350’s behavior when a master abort
0
termination occurs in response to a transaction
initiated by Tsi350 on either the primary or secondary
PCI interface.
0 = Tsi350 asserts TRDY_b on the initiator bus for
delayed transactions, and FFFF FFFFh for read
transactions. For posted write transactions,
P_SERR_b is not asserted.
1 = Tsi350 returns a target abort on the initiator bus
for delayed transactions. For posted write
transactions, Tsi350 asserts P_SERR_b if the
SERR_b enable bit is set in the command register.
Reset value: 0.
22
Secondary bus reset
R/W
Controls S_RST_b on the secondary interface.
0
0 = Tsi350 de-asserts S_RST_b.
1 = Tsi350 asserts S_RST_b.
When S_RST_b is asserted, the data buffers and the
secondary interface are initialized back to reset
conditions. The primary interface and configuration
registers are not affected by the assertion of
S_RST_b.
Reset value: 0.
Integrated Device Technology
www.idt.com
Tsi350 User Manual
January 10, 2014