TSI350 Datasheet, PDF (130/163 Pages) Integrated Device Technology – This chapter discusses the following

130
15. Registers > PCI-to-PCI Bridge Standard Configuration Registers
Bit
Name
Type
Description
Reset
Value
30
Received
R/W1C
This bit is set to 1 when Tsi350 detects the assertion of 0
system error
S_SERR_b on the secondary interface.
Reset value: 0.
31
Detected parity error R/W1C
This bit is set to 1 when Tsi350 detects an address or 0
data parity error on the secondary interface.
Reset value: 0.
Tsi350 User Manual
January 10, 2014
Integrated Device Technology
www.idt.com