TSI350 Datasheet, PDF (50/163 Pages) Integrated Device Technology – This chapter discusses the following

50
3.3.1
3. Address Decoding > Address Decoding
• The VGA snoop bit
This section provides information on the I/O address registers and ISA mode. “VGA Mode” on
page 55 provides information on the VGA modes.
To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command
register in Tsi350 configuration space. If the I/O enable bit is not set, all I/O transactions initiated on
the primary bus are ignored. To enable upstream forwarding of I/O transactions, the master enable bit
must be set in the command register. If the master enable bit is not set, Tsi350 ignores all I/O and
memory transactions initiated on the secondary bus. Setting the master enable bit also allows upstream
forwarding of memory transactions.
If any Tsi350 configuration state affecting I/O transaction forwarding is changed by a
configuration write operation on the primary bus at the same time that I/O transactions are
ongoing on the secondary bus, Tsi350 response to the secondary bus I/O transactions is not
predictable. Configure the I/O base and limit address registers, ISA enable bit, VGA mode
bit, and VGA snoop bit before setting the I/O enable and master enable bits, and change them
subsequently only when the primary and secondary PCI buses are idle.
Base and Limit Address Registers
Tsi350 implements one set of I/O base and limit address registers in configuration space that define an
I/O address range for downstream forwarding. Tsi350 supports 32-bit I/O addressing, which allows I/O
addresses downstream of Tsi350 to be mapped anywhere in a 4 GB I/O address space.
I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are
forwarded downstream from the primary PCI bus to the secondary PCI bus. I/O transactions with
addresses that fall outside this range are forwarded upstream from the secondary PCI bus to the
primary PCI bus.
The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/O
limit address. When the I/O range is turned off, all I/O transactions are forwarded upstream, and no I/O
transactions are forwarded downstream.
Tsi350 I/O range has a minimum granularity of 4 kB and is aligned on a 4 kB boundary. The maximum
I/O range is 4 GB in size.
The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at
address 30h. The top 4 bits of the 8-bit field define bits [15:12> of the I/O base address. The bottom 4
bits read only as 1h to indicate that Tsi350 supports 32-bit I/O addressing. Bits [11:0> of the base
address are assumed to be 0, which naturally aligns the base address to a 4 kB boundary.
The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define
AD[31:16> of the I/O base address. All 16 bits are read/write. After primary bus reset or chip reset, the
value of the I/O base address is initialized to 0000 0000h.
Tsi350 User Manual
January 10, 2014
Integrated Device Technology
www.idt.com