TSI350 Datasheet, PDF (27/163 Pages) Integrated Device Technology – This chapter discusses the following

2. PCI Interface > Transaction Phases
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2.2
2.2.1
2.2.1.1
2.2.1.2
Transaction Phases
Address Phase
The standard PCI transaction consists of one or two address phases, followed by one or more data
phases. An address phase always lasts one PCI clock cycle. The first address phase is designated by an
asserting (falling) edge on the FRAME_b signal. The number of address phases depends on whether
the address is 32 bits or 64 bits.
Single Address Phase
A 32-bit address uses a single address phase. This address is driven on AD[31:0], and the bus
command is driven on C/BE_b[3:0]. Tsi350 supports the linear increment address mode only, which is
indicated when the lower two address bits are equal to 0. If either of the lower two address bits is
nonzero, Tsi350 automatically disconnects the transaction after the first data transfer.
Dual Address Phase
Dual address transactions are PCI transactions that contain the following two address phases specifying
a 64-bit address:
• The first address phase is denoted by the asserting edge of FRAME_b.
• The second address phase always follows on the next clock cycle.
The first address phase contains the dual address command code on the C/BE_b[3:0] lines, and the low
32 address bits on the AD[31:0] lines. The second address phase consists of the specific memory
transaction command code on the C/BE_b[3:0] lines and the high 32 address bits on the AD[31:0]lines.
In this way, 64-bit addressing can be supported on 32-bit PCI buses.
The PCI-to-PCI Bridge Architecture Specification supports the use of dual address transactions in the
prefetchable memory range only. Tsi350 supports dual address transactions in both the upstream and
the downstream direction. Tsi350 supports a programmable 64-bit address range in prefetchable
memory for downstream forwarding of dual address transactions. Dual address transactions falling
outside the prefetchable address range are forwarded upstream, but not downstream. Prefetching and
posting are performed in a manner consistent with the guidelines given in this specification for each
type of memory transaction in prefetchable memory space.
Any memory transactions addressing the first 4 GB space should use a single address phase; that is, the
high 32 bits of a dual address transaction should never be 0.
Tsi350 responds only to dual address transactions that use the following transaction command codes:
• Memory Write
• Memory Write and Invalidate
• Memory Read
• Memory Read Line
Integrated Device Technology
www.idt.com
Tsi350 User Manual
January 10, 2014