TSI350 Datasheet, PDF (34/163 Pages) Integrated Device Technology – This chapter discusses the following

34
2.4.2
2.4.3
2.4.4
2. PCI Interface > Read Transactions
• For single D-word read transactions prefetching is ignored.
• In the case where there is a single request pending in the buffers and flow-through is established,
the maximum prefetch count value programmed at offset 0x44 is ignored
Prefetchable Read Transactions
A prefetchable read transaction is a read transaction where the Tsi350 performs speculative Dword
reads, transferring data from the target before it is requested from the initiator. This behavior allows a
prefetchable read transaction to consist of multiple data transfers. However, byte enable bits cannot be
forwarded for all data phases as is done for the single data phase of the non-prefetchable read
transaction.
Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as
for memory read transactions that fall into prefetchable memory space.
The amount of data that is prefetched depends on the type of transaction. The amount of prefetching
may also be affected by the amount of free buffer space available in the Tsi350, and by any read
address boundaries encountered.
Non-Prefetchable Read Transactions
A non-prefetchable read transaction is a read transaction where the Tsi350 requests 1–and only
1–Dword from the target and disconnects the initiator after delivery of the first Dword of read data.
Unlike prefetchable read transactions, the Tsi350 forwards the read byte enable information for the data
phase.
Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for memory
read transactions that fall into non-prefetchable memory space. If extra read transactions could have
side effects, for example, when accessing a FIFO, use non-prefetchable read transactions to those
locations. Accordingly, if it is important to retain the value of the byte enable bits during the data
phase, use non-prefetchable read transactions. If these locations are mapped in memory space, use the
memory read command and map the target into non-prefetchable (memory-mapped I/O) memory space
to utilize non-prefetching behavior.
Read Prefetch Address Boundaries
Tsi350 has internal read address boundaries on read prefetching. When a read transaction reaches one
of these aligned address boundaries, Tsi350 stops prefetching data, unless the target signals a target
disconnect before the read prefetch boundary is reached. When Tsi350 finishes transferring this read
data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator
completes the transaction before all prefetched read data is delivered. Any leftover prefetched data is
discarded.
Prefetchable read transactions in flow-through mode prefetch to the nearest aligned 4 kB address
boundary, or until the initiator de-asserts FRAME_b. “Delayed Read Completion on Initiator Bus ” on
page 36 describes flow-through mode during read operations.
Tsi350 User Manual
January 10, 2014
Integrated Device Technology
www.idt.com