TSI350 Datasheet, PDF (140/163 Pages) Integrated Device Technology – This chapter discusses the following

140
15. Registers > Device-Specific Configuration Registers
15.3.2
Bit
8
10:9
15:11
Diagnostic Control Register – Offset 0x40
W1S indicates that writing 1 in this bit position causes a chip reset to occur. Writing 0 has no effect.
• Dword address = 0x40
• Byte enable P_CBE_b[3:0] = xx0xb
Name
Chip reset
Test mode
Reserved
Type
R/W1S
R/W
R
Description
Reset
Value
Chip and secondary bus reset control.
0
1 = Causes Tsi350 to perform a chip reset. Data buffers,
configuration registers, and both the primary and
secondary interfaces are reset to their initial state. Tsi350
clears this bit once chip reset is complete. Tsi350 can then
be reconfigured.
Secondary bus reset S_RST_b is asserted and the
secondary reset bit in the bridge control register is set
when this bit is set. The secondary reset bit in the bridge
control register must be cleared in order to de-assert
S_RST_b.
Controls the testability of Tsi350’s internal counters.
0
These bits are used for chip test only. The value of these
bits controls which bytes of the counters are exercised:
00b = Normal functionality – all bits are exercised.
01b = Byte 1 is exercised.
10b = Byte 2 is exercised.
11b = Byte 0 is exercised.
Reset value: 00b.
Reserved. Returns 0 when read.
0
Tsi350 User Manual
January 10, 2014
Integrated Device Technology
www.idt.com