82V3012 Datasheet, PDF (27/32 Pages) Integrated Device Technology – T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

IDT82V3012
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
8 TIMING CHARACTERISTICS
8.1
TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS
Parameter
V_T
V_HM
V_LM
Description
Threshold Voltage
Rise and Fall Threshold Voltage High
Rise and Fall Threshold Voltage Low
CMOS
0.5V_DDD
0.7V_DDD
0.3V_DDD
Units
V
V
V
All Siganls
t_IRF,t_ORF
Timing Reference Points
V_HM
V_T
t_IRF,t_ORF
V_LM
Figure - 11 Timing Parameter Measurement Voltage Levels
Notes:
1. Voltages are with respect to ground (VSS) unless otherwise stated.
2. Supply voltage and operating temperature are as per Recommended Operating Conditions.
3. Timing for input and output signals is based on the worst case result of the CMOS thresholds.
8.2
INPUT/OUTPUT TIMING
Parameter
Description
t_RW Reference input pulse width high or low
t_IRF
t_R8D
t_R15D
t_R2D
t_R19D
t_F0D
t_F16S
t_F16H
t_F19S
t_F19H
t_C15D
t_C3D
t_C6D
t_C2D
t_C4D
t_C8D
t_C16D
Reference input rise or fall time
8 kHz reference input to F8o delay
1.544 MHz reference input to F8o delay
2.048 MHz reference input to F8o delay
19.44 MHz reference input to F8o delay
F8o to F0o delay
F16o setup to C16o falling
F16o hold to C16o falling
F19o setup to C19o falling
F19o hold to C19o falling
F8o to C1.5o delay
F8o to C3o delay
F8o to C6o delay
F8o to C2o
F8o to C4o
F8o to C8o delay
F8o to C16o delay
Min.
Typ.
Max.
Units
Test Conditions
51
ns
8 kHz, 1.544 MHz or 2.048 MHz
reference input
5
ns
19.44 MHz reference input
10
ns
8
ns
332
ns
253
ns
8
ns
118
121
124
ns
25
40
ns
25
40
ns
20
35
ns
20
35
ns
-3
0
+3
ns
-3
1.6
+3
ns
-3
1.6
+3
ns
-2
0
+2
ns
-2
0
+2
ns
-2
0
+2
ns
-2
0
+2
ns
Timing Characteristics
27
February 6, 2009