82V3012 Datasheet, PDF (15/32 Pages) Integrated Device Technology – T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

IDT82V3012
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
The 32.768 MHz signal is used by the E1_divider to generate five
types of clock signals (C2o, C4o, C8o, C16o and C32o) with nominal
50% duty cycle and six types of framing signals (F0o, F8o, F16o, F32o,
RSP and TSP).
The 24.704 MHz signal is used by the T1_divider to generate two
types of T1 signals (C1.5o and C3o) with nominal 50% duty cycle.
The 25.248 MHz signal is used by the C6_divider to generate a C6o
signal with nominal 50% duty cycle.
The 19.44 MHz signal is sent to an APLL, which outputs a 155.52
MHz signal. The 155.52 MHz signal is used by the C19_divider to
generate 19.44 MHz clock signals (C19o, C19POS and C19NEG) with
nominal 50% duty cycle and a framing signal F19o.
Additionally, the IDT82V3012 provides an output clock (C2/C1.5)
with the frequency controlled by the frequency selection pins Fx_sel0
and Fx_sel1 (see Table - 5 for details). If the selected reference input
(Fref0 or Fref1) is 8 kHz, 2.048 MHz or 19.44 MHz, the C2/C1.5 pin will
output a 2.048 MHz clock signal. If the selected reference input (Fref0 or
Fref1) is 1.544 MHz, the C2/C1.5 pin will output a 1.544 MHz clock
signal. The electrical and timing characteristics of this output (2.048
MHz or 1.544 MHz) is the same as that of C2o or C1.5o.
Table - 5 C2/C1.5 Output Frequency Control
Frequency Selection Pins
Fx_sel1
Fx_sel0
Frefx Input
Frequency
C2/C1.5 Output
Frequency
0
0
19.44 MHz
2.048 MHz
0
1
8 kHz
2.048 MHz
1
0
1.544 MHz
1.544 MHz
1
1
2.048 MHz
2.048 MHz
Note: ‘x’ can be 0 or 1, as selected by IN_sel pin.
IN_sel = 0: x = 0, Fref0 is the selected reference input. The frequency of Fref0
is determined by F0_sel0 and F0_sel1 pins.
IN_sel = 1: x = 1, Fref1 is the selected reference input. The frequency of Fref1
is determined by F1_sel0 and F1_sel1 pins.
2.8
OSC
The IDT82V3012 can use a clock as the master timing source. In the
Freerun mode, the frequency tolerance of the clock outputs is identical
to that of the source at the OSCi pin. For applications not requiring an
accurate Freerun mode, the tolerance of the master timing source may
be ±100 ppm. For applications requiring an accurate Freerun mode,
such as AT&T TR62411, the tolerance of the master timing source must
be no greater than ±32 ppm.
The desired capture range should be taken into consideration when
determining the accuracy of the master timing source. The sum of the
accuracy of the master timing source and the capture range of the
IDT82V3012 will always equal 230 ppm. For example, if the master
timing source is 100 ppm, the capture range will be 130 ppm.
For applications requiring ±32 ppm clock accuracy, the following
clock oscillator module may be used.
FOX F7C-2E3-20.0 MHz
Frequency: 20.0 MHz
Tolerance:
25 ppm 0°C to 70°C
Rise & Fall Time: 10 ns (0.33 V, 2.97 V, 15 pF)
Duty Cycle: 40% to 60%
For Stratum 3 application, the clock oscillator should meet the
following requirements:
Frequency: 20.0 MHz
Tolerance: ±4.6 ppm over 20 years life time
Drift:
±0.04 ppm per day @ constant temperature
±0.3 ppm over temperature range of 0 to 70°C
The output clock should be connected directly (not AC coupled) to
the OSCi input of the IDT82V3012, as shown in Figure - 8.
IDT82V3012
+3.3 V
OSCi
+3.3 V
20 MHz OUT
0.1 µF
GND
Figure - 8 Clock Oscillator Circuit
2.9
JTAG
The IDT82V3012 supports IEEE 1149.1 JTAG Scan.
2.10 RESET, LOCK AND TIE APPLICATION
A simple power-up reset circuit is shown as Figure - 9. The logic low
reset pulse is about 50 µs.
The resistor Rp is used for protection only and limits current into the
RST pin during power down. The logic low reset pulse width is not
critical but should be greater than 300 ns.
When the DPLL operates in Normal mode after power-up or reset,
the lock pin may indicate frequency lock before the output phase is
synchronized with the input. The phase lock requires 30 seconds (at
most) after frequency lock.
If users want to switch the input reference, it is highly recommended
to do the switch after phase lock, with TIE control block enabled.
After TIE control block is cleared, the DPLL requires some time for
the phase relationship to stabilize. In general, the phase lock requires 30
seconds (at most) after frequency lock.
2.8.1
CLOCK OSCILLATOR
When selecting a Clock Oscillator, numerous parameters must be
considered. This includes absolute frequency, frequency change over
temperature, output rise and fall times, output levels and duty cycle.
Functional Description
15
February 6, 2009