82V3012 Datasheet, PDF (11/32 Pages) Integrated Device Technology – T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

IDT82V3012
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
The mode changes between Normal (S1) and Auto-Holdover (S2)
are triggered by the Invalid Input Reference Detection Circuit and are
irrelative to the logic levels on the MODE_sel0 and MODE_sel1 pins. At
the stage of S1, if the input reference is invalid (out of the capture
range), the operating mode will be changed to Auto-Holdover (S2)
automatically. At the stage of S2, if no IN_sel transient occurs and the
input reference becomes valid, the operating mode will be changed back
to Normal (S1) automatically. If an IN_sel transient is detected at the
stage of S2, the operating mode will be changed to Short Time Holdover
(S4) with the TIE Control Block automatically disabled. Refer to “2.5
Invalid Input Signal Detection” for more information.
The mode changes between Normal (S1) and Short Time Holdover
(S4) are triggered by the IN_sel transient. At the stage of S1, if a voltage
transient occurs on the IN_sel pin, the operating mode will be changed
to Short Time Holdover (S4) automatically. At the stage of S4, if no
voltage transient occurs on the IN_sel pin, the operating mode will be
changed back to S1 automatically. See “2.3 Reference Input Switch” for
details.
When the operating mode is changed from one to another, the TIE
control block is automatically disabled as shown in Figure - 3, except the
changes from Short Time Holdover (S4), Holdover (S3) or Auto-
Holdover (S2) to Normal (S1). In the case of changing from S4, S3 or S2
to S1, the TIE control block is enabled or disabled by the TIE_en pin.
2.1.1
NORMAL MODE
The Normal mode is typically used when a slave clock source
synchronized to the network is required.
In this mode, the IDT82V3012 provides timing (C1.5o, C3o, C2o,
C4o, C8o, C16o, C19o, C32o) and synchronization (F0o, F8o, F16o,
F19o, F32o, TSP, RSP) signals. All these signals are synchronous to
one of the two input references. The nominal frequency of the input
reference can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz.
After reset, the IDT82V3012 will take 30 seconds at most to make
the output signals synchronous (phase locked) to the input reference.
Whenever the IDT82V3012 works in the Normal mode, the NORMAL
pin will be set to logic high.
2.1.2
FAST LOCK MODE
The Fast Lock mode is a submode of the Normal mode. It allows the
DPLL to lock to a reference more quickly than the Normal mode allows.
Typically, the locking time in the Fast Lock mode is less than 500 ms.
When the FLOCK pin is set to high, the Fast Lock mode will be
enabled.
2.1.3
HOLDOVER MODE
The Holdover mode is typically used for short duration (e.g., 2
seconds) while network synchronization is temporarily disrupted.
In the Holdover mode, the IDT82V3012 provides timing and
synchronization signals that are not locked to an external reference
signal, but are based on storage techniques. In the Normal mode, when
the output frequency is locked to the input reference signal, a numerical
value corresponding to the output frequency is stored alternately in two
memory locations every 30 ms. When the device is changed to the
Holdover mode, the stored value from between 30 ms and 60 ms is used
to set the output frequency of the device.
The frequency accuracy in the Holdover mode is ±0.025 ppm, which
corresponds to a worst case of 18 frame (125 µs per frame) slips in 24
hours. This meets the AT&T TR62411 and Telcordia GR-1244-CORE
Stratum 3 requirement of ±0.37 ppm (255 frame slips per 24 hours).
Whenever the IDT82V3012 works in the Holdover mode, the
HOLDOVER pin will be set to logic high.
2.1.4
FREERUN MODE
The Freerun mode is typically used when a master clock source is
required, or used when a system is just powered up and the network
synchronization has not been achieved.
In this mode, the IDT82V3012 provides timing and synchronization
signals which are based on the master clock frequency (OSCi) only, and
are not synchronized to the input reference signal.
The accuracy of the output clock is equal to the accuracy of the
master clock (OSCi). So if a ±32 ppm output clock is required, the
master clock must also be ±32 ppm. Refer to “2.8 OSC” for more
information.
Whenever the IDT82V3012 works in the Freerun mode, the
FREERUN pin will be set to logic high.
2.2
FREQUENCY SELECT CIRCUIT
The input reference can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44
MHz. The F0_sel1 and F0_sel0 pins select one of the four frequencies
for the reference input 0 (Fref0). The F1_sel1 and F1_sel0 pins select
one of the four frequencies for the reference input 1 (Fref1). See Table -
2 and Table - 3 for details.
The reference inputs Fref0 and Fref1 may have different frequencies
applied to them. Every time the frequency is changed, the device must
be reset to make the change effective.
Table - 2 Fref0 Frequency Selection
Frequency Selection Pins
F0_sel1
F0_sel0
Fref0 Input Frequency
0
0
19.44 MHz
0
1
8 kHz
1
0
1.544 MHz
1
1
2.048 MHz
Table - 3 Fref1 Frequency Selection
Frequency Selection Pins
F1_sel1
F1_sel0
0
0
0
1
1
0
1
1
Fref1 Input Frequency
19.44 MHz
8 kHz
1.544 MHz
2.048 MHz
2.3
REFERENCE INPUT SWITCH
The IDT82V3012 accepts two simultaneous reference signals Fref0
and Fref1, and operates on the falling edge (8 kHZ, 1.544 MHz and
2.048 MHz) or rising edge (19.44 MHz). One of the two reference
signals will be input to the device, as determined by the IN_sel pin. See
Functional Description
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February 6, 2009