82V3012 Datasheet, PDF (16/32 Pages) Integrated Device Technology – T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

IDT82V3012
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
IDT82V3012
RST
3.3 V
R
10 kΩ
Rp
1 kΩ
C
1 µF
Figure - 9 Power-Up Reset Circuit
2.11 POWER SUPPLY FILTERING TECHNIQUES
To achieve optimum jitter performance, power supply filtering is
required to minimize supply noise modulation of the output clocks. The
common sources of power supply noise are switching power supplies
and the high switching noise from the outputs to the internal PLL. The
82V3012 provides separate power pins: V_DDA and V_DDD. V_DDA pins are
for the internal analog PLL, and V_DDD pins are for the core logic as well
as I/O driver circuits.
To minimize switching power supply noise generated by the
switching regulator, the power supply output should be filtered with
sufficient bulk capacity to minimize ripple and 0.1 uF (0402 case size,
ceramic) capacitors to filter out the switching transients.
For the 82V3012, the decoupling for V_DDA and V_DDD are handled
individually. V_DDD and V_DDA should be individually connected to the
power supply plane through vias, and bypass capacitors should be used
for each pin. Figure - 10 illustrates how bypass capacitor and ferrite
bead should be connected to each power pin.
The analog power supply V_DDA should have low impedance. This
can be achieved by using one 10 uF (1210 case size, ceramic) and at
least two 0.1 uF (0402 case size, ceramic) capacitors in parallel. The 0.1
uF (0402 case size, ceramic) capacitors must be placed next to the
V_DDA pins and as close as possible. Note that the 10 uF capacitor must
be of 1210 case size, and it must be ceramic for lowest possible ESR
(Effective Series Resistance). The 0.1 uF should be of case size 0402,
which offers the lowest ESL (Effective Series Inductance) to achieve low
impedance towards the high speed range.
For V_DDD, at least three 0.1 uF (0402 case size, ceramic) and one 10
uF (1210 case size, ceramic) capacitors are recommended. The 0.1 uF
capacitors should be placed as close to the V_DDD pins as possible.
Please refer to evaluation board schematic for details.
3.3 V
SLF7028T-100M1R1
10 µF
3.3 V
SLF7028T-100M1R1
10 µF
IDT82V3012
37
V_DDA
0.1 µF
48
V_DDA
V_SS ¹²
V_SS ¹⁸
V_SS ²⁷
V_SS ³⁸
V_SS ⁴⁷
0.1 µF
13
V_DDD
0.1 µF
19
V_DDD
0.1 µF
26
V_DDD
0.1 µF
Figure - 10 IDT82V3012 Power Decoupling Scheme
Functional Description
16
February 6, 2009