82V3012 Datasheet, PDF (13/32 Pages) Integrated Device Technology – T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

IDT82V3012
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Ref1
Ref2
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Input Clock
Output Clock
Figure - 5 Reference Switch with TIE Control Block Enabled
Ref1
Ref2
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Input Clock
Output Clock
Figure - 6 Reference Switch with TIE Control Block Disabled
2.7
DPLL BLOCK
As shown in Figure - 7, the DPLL Block consists of a Phase Detector,
a Limiter, a Loop Filter, a Digital Control Oscillator and Divider.
2.7.1
PHASE DETECTOR (PHD)
In the Normal mode, the Phase Detector compares the virtual
reference signal from the TIE Control Circuit with the feedback signal
from the Frequency Select Circuit, and outputs an error signal
corresponding to the phase difference. This error signal is sent to the
Limiter circuit for phase slope control.
In the Freerun or Holdover mode, the Frequency Select Circuit, the
Phase Detector and the Limiter are inactive, and the input reference
signal is not used.
2.7.2
LIMITER
The Limiter is used to limit the phase slope. It ensures that the
maximum output phase slope is limited to 5 ns per 125 µs for all input
transient conditions. This well meets the AT&T TR62411 and Telcordia
GR-1244-CORE specifications, which specify the maximum phase slope
of 7.6 ns per 125 µs and 81 ns per 1.326 ms respectively.
Functional Description
13
February 6, 2009