ICS843N3960I Datasheet, PDF (2/20 Pages) Integrated Device Technology – Fourth Generation FemtoClock

ICS843N3960I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
FSEL0,
FSEL1
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3A.
3
OE
Input
Pullup Active HIGH output enable. LVCMOS/LVTTL interface levels.
4, 5
Q1, nQ1
Output
Differential output pair. 3.3V LVPECL interface levels.
6, 8, 14
7
V_EE
Power
CP
Output
Negative supply pins.
External loop filter capacitor output pin.
9
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to V_CC/2.
10
CLK
Input
Pulldown Non-inverting differential clock input.
11, 12
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
13
CLK_SEL
Input
Pulldown Input source control pin. LVCMOS/LVTTL interface levels. See Table 3C.
15
LOR
Output
Loss of Reference output pin. See LOR Functionality section.
16, 17
nQ0, Q0
Output
Differential output pair. 3.3V LVPECL interface levels.
18, 20
19
V_CC
V_CCA
Power
Power
Core supply pins.
Analog supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLDOWN
R_PULLUP
R_OUT
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Output Impedance
LOR
Test Conditions
Minimum
Typical
3.5
51
51
18
Maximum
Units
pF
kΩ
kΩ
Ω
ICS843N3960DGI REVISION B SEPTEMBER 24, 2012
2
©2012 Integrated Device Technology, Inc.