ICS843N3960I Datasheet, PDF (14/20 Pages) Integrated Device Technology – Fourth Generation FemtoClock

ICS843N3960I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843N3960I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843N3960I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{CC_MAX} * I_{EE_MAX} = 3.465V * 122mA = 422.73mW
• Power (outputs)_MAX = 30.0mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.0mW = 60.0mW
Total Power__MAX (3.465V, with all outputs switching) = 422.73mW + 60.0mW = 482.73mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 34.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.483W * 34.3°C/W = 101.56°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θ_JA for 20 Lead TSSOP, E-Pad Forced Convection
θ_JA by Velocity
Meters per Second
0
1
Multi-Layer PCB, JEDEC Standard Test Boards
34.3°C/W
29.9°C/W
2.5
28.4°C/W
ICS843N3960DGI REVISION B SEPTEMBER 24, 2012
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©2012 Integrated Device Technology, Inc.